Transaction Level Model Simulator for NoC-based MPSoC Platform

Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC) architecture is a promising SoC design solution, offering high computational power with lots of flexibilities. However, finding the optimal MPSoC architecture configuration remains an enormous challenge due to its high structural complexity and functional diversity. In this paper, we introduce a Transaction level NoC SIMulator (TraNSIM) to evaluate the performance of NoC based MPSoC architecture in the early design stage. Focusing on List Sphere Decoder (LSD) as a case study, we present the methodology to find an optimum multi-processor architecture, and demonstrate the performance variation with respect to different NoC topologies by using TranSIM. Key-Words: MPSoC, NoC, Transaction level model, SystemC.